Entry 14: Gated latches and flip-flops

In entry 13 we connected the output of a four D flip-flops (basic register) to the bus (through tri-state buffers). Now we want to do the reverse, connect the bus to the input of the register. The register designed in enty 9, QuadDFlipFlops,  will not quite work. 

This register will always load the data from the bus when the clock goes high. We need to be able to control when it will load data from the bus. We need an additional control line to the register, which we may call "load". The register shall only load data when load is high. It shall ignore the bus when load is low. A term for this feature is "Gated enable inputs" and the pin controlling the gate, the one I call "load", is also called "data enable".

Gated SR-latch

In order to make QuadDFlipFlops gated, we need to make a gated D flip-flop. D flip-flops are made from SR latches, so we need to go all the way back to these guys, and make them gated. This was the SR latches of the NAND type, that we created in entry 7:

We want to make this "gated" by adding a "Load pin". When Load is high (gate open), it should functions as before.  When Load is low (gate closed), there should be no change in the latch, no matter the values of Set and Reset. To accomplish this is simple, no need to ask Grok:

Note that when Load is 0, the two NAND gates on the left will always output 1 and there is "no change" in the latch. When Load is 1, the two NAND gates on the left will always output the values of Reset and Set. The latch then functions as before. This symbol makes sense for a gated NAND latch (L for Load):

Here is the full truth-table of the NAND latch with load.

These are the components I created:  

• "NandLatchGated" with precisely this functionality, see ACEL. 
• "NorLatchGated", a gated SR-latch based on NOR gates.

The pins are the same as for the andLatch and the NorLatch, but with the extra input pin "load". I am not going to test these, as they are very similar to the ungated versions, but you could certainly go ahead and do so. 

Gated D flip-flop

The D flip-flop we created in entry 8, DFlipFlop,  was "ungated". Creating a gated D flip-flop with an extra Load pin is simple. Just replace the slave SR latch with a gated one. The truth-table of a gated D flip-flop when Preset = 0 and Clear = 0 is then

As before, If Clear = 1, Q becomes 0 and if Preset = 1, Q becomes 1. This symbol makes sense for a gated D flip-flop (L for Load):

The name of this flip-flop in ACEL is DFlipFlopGated. Pins are:

• Input pin: D
• Input pin: Clock
• Input pin: Clear
• Input pin: Preset
• Input pin: Load
• Output pin: Q
• Output pin: Q_Bar.

Again, I am not going to test this, as it is similar to the ungated version. I assume it will work.

In the next entry, I will create a new register based on four gated D flip-flops. I will also add four tri-state buffers to the output so that the output can be connected directly to the bus.