Entry 15: Register version 2: gated and bus-friendly

A better register

In entry 9, we created QuadDFlipFlop, a first version of a register. Starting from this design, let's replace the ungated D flip-flops with gated ones, and add four tri-state buffers to the output pins. We then have a register we can connect to a data bus.

Here is the schematics of what I will build.

This component will be called a FourBitRegister, see ACEL.

• D0-D3 are data input pins, connected to the data line D of the D flip-flops.
• Load is an input pin, controlling all the gates of the D flip-flops.
• Clear is an input pin, setting all the D flip-flops to Q = 0.
• Clock is an input pin, a common clock signal for all the D flip-flops.
• Write is an input pin, a common "enable" for all the tri-state buffers.
• Q0-Q3 are output pins, the data stored in the D flip-flops. These are not tri-state.
• W0-W3 are tri-state output pins. When Write = 0 they are in state Z ("disconnected"). When Write = 1, W = Q. 

74LS173

The design of FourBitRegister is very similar to 74LS173/74HC173:

• 1D-4D are the "D0-D3"
• 1Q-4Q are teh "W0-W3)
• M and N together is the "Enable"
• G1 and G2 together is the "Load"

74LS173 does not have non-tri-state outputs.

Moving data from one register to another using the data bus

To test this out, we connect two registers (A and B) to a data bus. The goal is to move data from register A to register B. We also need DIP-switches to get data onto the bus (through tri-state buffers). This is the schematics.

Code:

  //Define chips

  auto* registerA = new FourBitRegister((char*)("Register A"));

  auto* registerB = new FourBitRegister((char*)("Register B"));

  auto* buffers = new QuadThreeStateSwitches();

  auto* bus = new BusLineFour();

  //Add all chips to be emulated here

  Chip* chips[] = {

    registerA, registerB, buffers, bus

  };

  //Add all connections here

  ConnectionBase* connections[] = {

    //Connect DIP switches to pins 2-5

    new ConnectionFour(ard, 2, buffers->D, 1),

    new ConnectionFour(buffers->W, bus->X),

    new Connection(ard, 6, buffers->Enable),

    //Register A

    new Connection(ard, 7, registerA->Clock),

    new Connection(ard, 8, registerA->Load),

    new Connection(ard, 9, registerA->Write),

    new ConnectionFour(registerA->W, bus->X),

    new ConnectionFour(bus->W, registerA->D),

    //Register B

    new Connection(ard, 7, registerB->Clock),

    new Connection(ard, 22, registerB->Load),

    new Connection(ard, 23, registerB->Write),

    new ConnectionFour(registerB->W, bus->X),

    new ConnectionFour(bus->W, registerB->D),

  };

Try this out yourself on Wokwi, project "Two registers and a bus".