ACEL

SR-latch, NOR version

Alternative name: RS-latch, NOR latch.

Design:

• Name: NorLatch
• Input: Set, Reset
• Output: Q, Q_Bar
• Entry: 4
• Chip: ?

SR-latch, NAND version

Alternative name: NAND latch.

Note: Sometimes with a bar on top of R and S.

Design:

• Name: NandLatch
• Input: Set, Reset
• Output: Q, Q_Bar
• Entry: 7
• Chip: 74LS279 (x4)

D flip-flop

Design:

• Name: DFlipFlop
• Input: D, Clock
• Output: Q, Q_Bar
• Entry: 8
• Chip: 74LS74 or 74HC74 (x2)
• Note: 74HC74 has two additional input pins for each flip-flop: Preset and Clear

4 bit register, version 1

Design:

• Name: FourBitRegister
• Input: D[4] (D[0],D[1], D[2], D[3]), Clock
• Output: Q[4]
• Entry: 9
• Chip: 74LS173 (has additional features)

Tri-state buffer

Design: transistor.

• Name: ThreeStateSwitch
• Input: D, E
• Output: W
• Entry 12
• Chip: 74LS126 and 74LS125 (inverted E)

Four tri-state buffers

Design:

• Name: FourThreeStateSwitches
• Input: D[4], E
• Output: W[4]
• Entry 13
• Chip: 74LS126 and 74LS125 (inverted E)

Gated SR-latch, NOR version

Alternative name: gated NOR latch.

Design: Similar to gated NAND latch.

• Name: NorLatchGated
• Input: Set (S), Reset (R), Load (L)
• Output: Q, Q_Bar
• Entry: 14
• Chip: ?

Gated SR-latch, NAND version

Alternative name: NAND latch.

Note: Sometimes with a bar on top of R and S.

Design:

• Name: NandLatchGated
• Input: Set (S), Reset (R), Load (L)
• Output: Q, Q_Bar
• Entry: 14
• Chip: ?

Gated D flip-flop

Design: Similar to regular D flip-flop but with gated SR-latch

• Name: DLatchGated
• Input: Data (D), Load (L), Clock(CLK)
• Output: Q, Q_Bar
• Entry: 14
• Chip: ?

4 bit register, version 2

Design:

• Name: FourBitRegisterGatedTriState
• Input: D[4], Load (L), Clock(CLK)
• Output: Q[4], W[4]
• Entry: 15
• Chip: 74LS173