Introduction
In the previous entry, we looked at instructions and the instruction register. The current goal is to build a processor that can run the following program:
This program adds 5 and 3 and displays the result on LEDs. Also, we decided that the processor should support the following instructions:
In order to support these instructions, we need the following components (as a starting point):
- See entry 26 and 27 for the program counter
- See entry 21 for the memory system
- See entry 28 for the instruction register
"A, B, OUT and ALU" (see entry 23):
- Program counter:
- COUNT (increase count)
- PCL (loads from the data bus)
- PCW (writes to the address bus)
- Memory system:
- MARL (loads MAR from the address bus)
- MDRL (loads MDR from the data bus)
- RAML (loads data stored in MDR at address stored in MAR into RAM)
- RAMW (writes data to data bus and address bus)
- Instruction register
- IRL (loads from the data bus)
- A, B, OUT and ALU
- RAL (loads register A from the data bus)
- RBL (loads register B from the data bus)
- ROL (loads register OUT from the data bus and activates LEDs)
- RAW (writes A to the data bus)
- ALUW (writes ALU to the data bus)
The next step is to build an "instruction decoder" so that the processor can "run the program" by itself.
I didn't really follow the first answer by Grok on "instruction decoding" but the concept "T-state" was mentioned. So, let's start there.
T-states
"Is the instruction decoder related to "T states"? Grok:
Instruction Set (Proposed): (Removed, see table above)
Instruction Format:
- NOP, ADD, HLT, MOV B,A, MOV OUT,A: Single 4-bit opcode (4 bits total).
- LDA, STA, JMP: Opcode + 4-bit address (8 bits, two fetches).
What Are T-States?
- Definition: A T-state (Timing state) is one clock cycle in a processor’s operation, representing the smallest unit of time for executing part of an instruction. In the 8085, each instruction takes multiple T-states (e.g., LDA 2034H = 13 T-states), split across fetch, decode, and execute phases.
- Purpose: T-states break down instruction execution into steps:
- Fetch opcode from RAM.
- Fetch operands (e.g., address for LDA).
- Decode opcode.
- Execute (e.g., load, add, store).
Instruction Decoder and T-States
- Relation: The instruction decoder is intimately tied to T-states because it generates control signals that determine what happens in each T-state (e.g., clocking IR, enabling ALU, writing RAM). Each instruction requires a specific sequence of T-states, and the decoder ensures the right signals are active at the right time.
My summary
- Each instruction requires a number of T-states to complete. For example, an instruction needing 4 T-states takes four clock cycles to execute.
- T-states start with T-state 1, followed by T-state 2, and so on. After the final T-state, the processor returns to T-state 1 to fetch the next instruction.
- In each T-state, relevant control pins (or, as they are also called, control signals) are set to perform specific actions, remaining stable throughout the T-state and changing at the start of the next.
- A T-state begins on the clock’s falling edge (high-to-low from the 555 timer) and lasts until the next falling edge, ensuring that the control pins remain stabilized on the clock's rising edge (low-to-high). In this example, instruction 1 has 4 T-states and instruction 2 has 3 T-states:
- For example, to move Register A’s contents to Register B in one T-state, the decoder enables A’s "Write" pin (RAW) and B’s "Load" pin (RBL) on the clock’s falling edge. A's data immediately goes on the data bus. However, B latches the data first on the following clock’s rising edge. This gives register A plenty of time to put the data onto the bus, ensuring a valid transfer.
- T-state 1 is identical for all instructions. The Instruction Register (IR) doesn’t yet hold the opcode. Control signals are set to transfer the Program Counter (PC) value to the Memory Address Register (MAR). The decoder sets PCW = 1 (PC writes to the address bus), and MARL = 1 (MAR loads from the address bus).
- T-state 2 is also universal. Here, the opcode is moved from RAM to the IR, and the PC is incremented. RAM already has the correct address, due to T-state 1. Therefore, in T-state 2, the decoder sets RAMW = 1 (RAM writes data to both buses), IRL = 1 (IR loads from the data bus), and COUNT = 1 (PC increments its count).
- T-state 3 and beyond depend on the opcode in the IR. For NOP, T-state 3 is idle, and the processor returns to T-state 1 for the next instruction’s fetch.
- For MOV B,A, T-state 3 sets RAW = 1 and RBL = 1 as discussed in the example above. No further action is needed, so it returns to T-state 1 for the next instruction.
- Thus, for all eight instructions—NOP, LDA, ADD, STA, JMP, HLT, MOV B, A, MOV OUT, A—we define how the decoder sets control signals in T-state 3 onward, while T-states 1 and 2 are uniformly handled.
Here is a complete list of control signals for all instructions in all T-states:
T-state 1: move the program count to MAR. T-state 2: move the opcode to IR and increase PC.
For example, consider STA. Since the PC was incremented in T-state 2, it is now pointing at the address at which to store the A register. So we move this address to MAR in T-state 3. In T-state 4, the decoder sets RAML = 1 and RAM will immediately load the data found in MDR into the correct address (the address in MAR). This is not the correct data, but that is OK. It also sets RAW = 1 so that the A register goes on the data bus. Since is sets MDRL = 1, MDR will load the correct data on the rising clock edge. RAM will then immediately write this (correct data) into the correct address. COUNT = 1 so the the PC increments, it will now point at the next opcode.
The next question is then, how do we build an instruction decoder which, depending on T-state and instruction, sets the correct control signals? Grok:
Next, let's figure out how ROM differs from RAM and then design the instruction decoder. Hopefully we can then make the processor run programs, like the one above.. in the next entry.
